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On-chip networks NoCs used in multiprocessor systems-on-chips MPSoCs pose significant challenges to both on-line dynamic and off-line static real-time scheduling approaches They have large numbers of potential contention points have limited internal buffering capabilities and network control operates at the scale of small data packets Therefore efficient resource allocation requires scalable algorithms working on hardware models with a level of detail that is unprecedented in real-time scheduling We consider in this thesis a static scheduling approach and we target massively parallel processor arrays MPPAs which are MPSoCs with large numbers hundreds of processing cores We first identify and compare the hardware mechanisms supporting precise timing analysis and efficient resource allocation in existing MPPA platforms We determine that the NoC should ideally provide the means of enforcing a global communications schedule that is computed off-line before execution and which is synchronized with the scheduling of computations on processors On the software side we propose a novel allocation and scheduling method capable of synthesizing such global computation and communication schedules covering all the execution communication and memory resources in an MPPA To allow an efficient use of the hardware resources our method takes into account the specificities of MPPA hardware and implements advanced scheduling techniques such as pre-computed preemption of data transmissions We evaluate our technique by mapping two signal processing applications for which we obtain good latency throughput and resource use figures

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Reconciling performance and predictability on a noc-based mpsoc using off-line scheduling techniques

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with Multiprocesseurs-sur-puce (many-coeur) as keyword