Progress in the digital multimedia technologies during the last decade has offered many facilities in the transmission, reproduction, and manipulation of data. However, this advancement has also brought the problem such as copyright protection for content providers. Digital watermarking is a proposed solution for copyright protection for multimedia. The goal of hardware assisted watermarking is to achieve low power usage, real-time performance, reliability, and ease of integration with existing consumer electronic devices. An efficient architecture for transform domain watermarking using quantization approach is proposed here. This architecture is optimized using pipelining. The main objective of this paper is to propose a very-large-scale integration (VLSI) architecture for robust and blind image watermarking chip. Watermarking architectures with and without pipeline are synthesized using Xilinx's ISE for a field-programmable gate array (FPGA), and then semi-custom integrated chip is designed using UMC 0.18 mu m technology standard cell library for both these architectures. The proposed optimized pipelined watermarking encoder core requires 0.027 mm(2) area and 0.074 mW power.