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Run-Time-Reconfigurable Multi-Precision Floating-Point Matrix Multiplier Intellectual Property Core on FPGA

Authors
  • Arish, S.1
  • Sharma, R. K.1
  • 1 National Institute of Technology Kurukshetra, School of VLSI Design and Embedded Systems, Kurukshetra, Haryana, India , Kurukshetra (India)
Type
Published Article
Journal
Circuits, Systems, and Signal Processing
Publisher
Springer US
Publication Date
May 24, 2016
Volume
36
Issue
3
Pages
998–1026
Identifiers
DOI: 10.1007/s00034-016-0335-2
Source
Springer Nature
Keywords
License
Yellow

Abstract

In today’s world, high-power computing applications such as image processing, digital signal processing, graphics, robotics require enormous computing power. These applications use matrix operations, especially matrix multiplication. Multiplication operations require a lot of computational time and are also complex in design. We can use field-programmable gate arrays as low-cost hardware accelerators along with a low-cost general-purpose processor instead of a high-cost application-specific processor for such applications. In this work, we employ an efficient Strassen’s algorithm for matrix multiplication and a highly efficient run-time-reconfigurable floating-point multiplier for matrix element multiplication. The run-time-reconfigurable floating-point multiplier is implemented with custom floating-point format for variable-precision applications. A very efficient combination of Karatsuba algorithm and Urdhva Tiryagbhyam algorithm is used to implement the binary multiplier. This design can effectively adjust the power and delay requirements according to different accuracy requirements by reconfiguring itself during run time.

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