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N-Polar Deep Recess MISHEMTs for mm-Wave Applications

Authors
  • Wienecke, Steven Michael
Publication Date
Jan 01, 2018
Source
eScholarship - University of California
Keywords
Language
English
License
Unknown
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Abstract

GaN based high electron mobility transistors (HEMTs) have emerged as a leading technology for mm-wave (30-300 GHz) wireless applications. Specifically, great interest has been shown in GaN transistors for high power transmitter applications in the W-band portion of the frequency spectrum (75-110GHz) where atmospheric attenuation of RF signals experiences a local minimum. To date, reports on W-band GaN HEMTs and monolithic microwave integrated circuits (MMICs) have primarily featured devices fabricated in the Ga-Polar (0001) orientation. In this work, the advantages of N-Polar GaN are exploited to produce a metal-insulator-semiconductor (MIS-HEMT) exhibiting (at the time) record high power amplification performance at 94 GHz.The key difference between Ga-Polar and N-Polar HEMTs is the orientation of the polarization fields. In N-Polar, the field orientation enables the fabrication of a novel recessed gate structure with the addition of an unintentionally doped (UID) GaN cap layer in the device access regions. This GaN cap serves a dual purpose. First, it effectively removes the DC-to-RF dispersion commonly seen in III-N transistors (dispersion in this sense refers to the phenomena where the device’s large signal RF power performance is significantly worse than that predicted from static DC measurements). The GaN cap removes this dispersion with a smaller capacitive penalty than traditional methods typically used in Ga-Polar transistors. Secondly, the GaN cap acts to reduce surface depletion, significantly reducing sheet resistance in the access regions. By reducing both the parasitic resistive and capacitive elements of the transistor, excellent large signal RF performance is achieved at very high frequencies. In this work, the device concept is introduced and the fabrication procedure is detailed. Several aspects of the device structure are examined, optimized, and record (at the time) performance results are presented.

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