A Novel Approach in Application Mapping for Two Dimensional Wireless Network-On-Chip (WiNoC) in Power Reduction

Affordable Access

Download Read

A Novel Approach in Application Mapping for Two Dimensional Wireless Network-On-Chip (WiNoC) in Power Reduction

Jury members
  • hedayati
Defense Date
Jan 14, 2018


The reason for the growing interest in networks on chips (NoCs) can be explained by looking at the evolution of integrated circuit technology and at the ever-increasing requirements on electronic systems. The integrated microprocessor has been a landmark in the evolution of computing technology. Whereas it took monstrous efforts to be completed, it appears now as a simple object to us. Indeed, the microprocessor involved the connection of a computational engine to a layered memory system, and this was achieved using busses. In the last decade, the frontiers of integrated circuit design opened widely. On one side, complex application-specific integrated circuits. Networkon- chip (NoC) has evolved as a viable solution to the communication problem between cores in a system-on-chip (SoC). System cost, in terms of area, delay, power, and so on, has contributions from both computation and communication requirements. Individual cores can be designed efficiently to make computation faster, but communication may become a bottleneck. As discussed in all chapters, the solution is influenced by several factors. The first and foremost issue is the topology in which routers are to be connected. While regular topologies, such as mesh and tree, make the design process simpler with predictable link delay and power consumption values, irregular application-specific topologies are expected to produce better performance. Individual routers should be simple with modules, such as ports, routing logic, arbiter, and channel allocator. Design of routing algorithm plays an important role, as it has to be free from deadlock and livelock problems, which may route in a shortest path through the network. Performance of such a network is often evaluated with the help of simulators and traffic generators. Apart from application-specific traffic, networks are often evaluated using uniform, self-similar, hot spot, and other types of traffic. For regular topologies, cores of an application are mapped onto individual routers using some mapping techniques. The mapped core gets attached to that router and all communication to and from the core is made through that router. The mapping problem is NP-hard; however, many heuristic strategies have been developed for the same. However, to achieve better performance, application-specific NoC architectures are evolved. Multi-application NoC design calls for a reconfigurable architecture, in which the same network resources are reused for different applications. The power consumed by the NoC in either case can be reduced using various strategies, such as encoding, serialization, and clock gating. A related issue is that of reliability of the system. Electromagnetic interference, synchronization failure, and soft errors come up as challenges to a reliable system operation. Testing of such system requires testing individual cores, routers, and links. The wireless communication alleviates the latency and energy dissipation issues of conventional technologies, and also solves the complex interconnect routing and placement problems. Multi-hop communication of traditional technologies can be converted into a single hop, resulting in significant saving in delay for communication. This seminar is going to introduce these concepts in NoC field. In this thesis we proposed and examined a novel approach to network on chip which is wireless approach, which make improvement in delay, Energy and power.

Report this publication


Seen <100 times
Downloaded <100 times