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Non-destructive laboratory-based X-ray diffraction mapping of warpage in Si die embedded in IC packages

Authors
  • Wong, C.S.
  • Bennett, N.S.
  • Manessis, D.
  • Danilewsky, A.
  • McNally, P.J.1, 2, 3, 4, 5, 6, 7, 8, 9
  • 1 Nanomaterials Processing Laboratory
  • 2 School of Electronic Engineering
  • 3 Dublin City University
  • 4 Fraunhofer IZM Berlin
  • 5 Microperipheric Research Center
  • 6 Berlin Center of Advanced Packaging
  • 7 Kristallographie
  • 8 Institut für Geowissenschaften
  • 9 Albert-Ludwigs-Universität
Type
Published Article
Journal
Microelectronic Engineering
Publisher
Elsevier
Publication Date
Jan 01, 2013
Accepted Date
Dec 10, 2013
Volume
117
Pages
48–56
Identifiers
DOI: 10.1016/j.mee.2013.12.020
Source
Elsevier
Keywords
License
Unknown

Abstract

Reliability issues as a consequence of thermal/mechanical stresses created during packaging processes have been the main obstacle towards the realisation of high volume 3D Integrated Circuit (IC) integration technology for future microelectronics. However, there is no compelling laboratory-based metrology that can non-destructively measure or image stress/strain or warpage inside packaged chips, System-on-Chip (SoC) or System-in-Package (SiP), which is identified as a requirement by the International Technology Roadmap for Semiconductors (ITRS). In the work presented here, a triple-axis Jordan Valley Bede D1 X-ray diffractometer is used to develop a novel lab-based technique called X-ray diffraction 3-dimensional surface modelling (XRD/3DSM) for non-destructive analysis of manufacturing process-induced stress/warpage inside completely encapsulated packaged chips. The technique is demonstrated at room temperature and at elevated temperatures up to 115°C by in situ XRD annealing experiments. The feasibility of this technique is confirmed through the characterisation of die stress inside encapsulated commercially available ultra-thin Quad Flat Non-lead (QFN) packages, as well as die stress in embedded QFN packages at various stages of the chip manufacturing process.

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