This paper presents new 3D-TRL structures for the THROUGH and the LINE standard for on-wafer calibration. Thanks to these structures the reference plane after calibration is defined at the lowest metal layer of the Back-End-of-Line for a given Silicon technology, so very close to the device under test. Results for transit frequency characterization of a hetero-junction bipolar transistor (HBT) are compared to standard calibration and deembedding techniques. We show that the use of the new structures gives the most accurate results. In addition, less test structures are needed and the results are more robust and less noisy.