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A neural network learning algorithm tailored for VLSI implementation.

Authors
  • Hollis, P W
  • Paulos, J J
Type
Published Article
Journal
IEEE transactions on neural networks / a publication of the IEEE Neural Networks Council
Publication Date
Jan 01, 1994
Volume
5
Issue
5
Pages
784–791
Identifiers
PMID: 18267851
Source
Medline
License
Unknown

Abstract

This paper describes concepts that optimize an on-chip learning algorithm for implementation of VLSI neural networks with conventional technologies. The network considered comprises an analog feedforward network with digital weights and update circuitry, although many of the concepts are also valid for analog weights. A general, semi-parallel form of perturbation learning is used to accelerate hidden-layer update while the infinity-norm error measure greatly simplifies error detection. Dynamic gain adaption, coupled with an annealed learning rate, produces consistent convergence and maximizes the effective resolution of the bounded weights. The use of logarithmic analog-to-digital conversion, during the backpropagation phase, obviates the need for digital multipliers in the update circuitry without compromising learning quality. These concepts have been validated through network simulations of continuous mapping problems.

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