The Hardware/Software (HW/SW) architectural exploration has become a key component of System on Chip (SoC) design modeling. The insufficient power and timing analysis capabilities at early stages of the design flow limit the optimized modeling. Thus, pushed by the need to improve that shortage and inspired by the numerous studies on Electronic System Level (ESL) modeling, we introduce a novel ESL methodology that combines power and performance estimation in one unified framework. In this paper, we present our new approach applied and tested on an NXP proprietary switch matrix/interconnect system used in i.MX8 series of SoCs. Our model is based on SystemC-TLM2.0 and make use of PwClkARCH library for power management. This framework allows us to develop a SoC transaction level model (TLM) written exclusively in C++/SystemC-TLM2.0 and to extract power consumption and performance metrics after the simulation. This modeling approach allows a strong separation between the functional SystemC/TLM model and its power intent description. Only a few pieces of code must be added to performance model to hook power model to it. Moreover, it makes the code easier to debug and maintain.