A significant improvement of the light load conversion efficiency in integrated CMOS DC–DC converters using pulse-width modulation (PWM) at constant switching frequencies above 1 MHz can be obtained by implementing dynamic width controlling (DWC) of the power transistors. The parallel implementation of DWC uses equally sized power cells, each containing the power transistor and its gate driver stages. The power cells are connected together in a parallel arrangement to limit the propagation delays and to avoid the transmission gates used in serial implementations. Due to this, higher switching frequencies can be realized. Advanced simulations were performed with Cadence Spectre combined with Mathematica to investigate the conversion efficiency improvement potential offered by DWC. With DWC, an absolute increase of the light load conversion efficiency as high as 29% can be achieved for switching frequencies in the range 1–10 MHz. Further, a conversion efficiency higher than 80% can be provided over roughly two decades of load current for a DC–DC converter operating at a switching frequency of 10 MHz. Experimental results obtained from a synchronous buck converter designed in a 0.18 μm CMOS technology and switched at 2 MHz in continuous conduction mode (CCM) have demonstrated an improvement of the light-load conversion efficiency of about 25%.