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JFET SOS devices: Processing and gamma radiation effects

Authors
  • nie, jp
  • liu, zl
  • zj, he
  • yu, f
  • gh, li
  • chinese, jp r nie
Publication Date
Jan 01, 1998
Source
Knowledge Repository of SEMI,CAS
Keywords
License
Unknown
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Abstract

A process for fabricating n channel JFET/SOS (junction field-effect transistors on silicon-on-sapphire) has been researched. The gate p(+)n junction was obtained by diffusion, and the conductive channel was gotten by a double ion implantation. Both enhancement and depletion mode transistors were fabricated in different processing conditions. From the results of the Co-50 gamma ray irradiation experimental we found that the devices had a good total dose radiation-hardness. When the tot;ll dose was 5Mrad(Si), their threshold voltages shift was less than 0.1V. The variation of transconductance and the channel leakage current were also little.

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