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A High-Voltage-Tolerant and Precise Charge-Balanced Neuro-Stimulator in Low Voltage CMOS Process.

Authors
  • Luo, Zhicong
  • Ker, Ming-Dou
Type
Published Article
Journal
IEEE Transactions on Biomedical Circuits and Systems
Publisher
Institute of Electrical and Electronics Engineers
Publication Date
Dec 01, 2016
Volume
10
Issue
6
Pages
1087–1099
Identifiers
DOI: 10.1109/TBCAS.2015.2512443
PMID: 27046880
Source
Medline
License
Unknown

Abstract

This paper presents a 4 × VDD neuro-stimulator in a 0.18- μm 1.8 V/3.3 V CMOS process. The self-adaption bias technique and stacked MOS configuration are used to prevent transistors from the electrical overstress and gate-oxide reliability issue. A high-voltage-tolerant level shifter with power-on protection is used to drive the neuro-stimulator The reliability measurement of up to 100 million periodic cycles with 3000- μA biphasic stimulations in 12-V power supply has verified that the proposed neuro-stimulator is robust. Precise charge balance is achieved by using a novel current memory cell with the dual calibration loops and leakage current compensation. The charge mismatch is down to 0.25% over all the stimulus current ranges (200-300 μA) The residual average dc current is less than 6.6 nA after shorting operation.

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