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Design optimization of gate-silicided ESD NMOSFETs in a 45 nm bulk CMOS technology

Authors
Journal
Microelectronics Reliability
0026-2714
Publisher
Elsevier
Publication Date
Volume
49
Issue
12
Identifiers
DOI: 10.1016/j.microrel.2009.06.051

Abstract

Abstract Decrease of the drain silicide-blocking-to-gate spacing in gate-silicided-ESD-NMOSFETs improves the TLP and HBM failure levels up to 30%, while no effect is observed when decreasing the source silicide-blocking-to-gate spacing. Failure analysis and simulation results show that current crowding in the drain silicide region accounts for the difference in failure current for the devices.

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