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A hardware implementation of distributed network protocol

Authors
Journal
Computer Standards & Interfaces
0920-5489
Publisher
Elsevier
Publication Date
Volume
27
Issue
3
Identifiers
DOI: 10.1016/j.csi.2004.07.003
Keywords
  • Dnp
  • Verilog Hdl
  • Fpga
  • Supervisory Control And Data Acquisition (Scada)
  • Soc
Disciplines
  • Communication
  • Computer Science
  • Design

Abstract

Abstract This paper presents a promising solution for the implementation of distributed network protocol version 3 (DNP3). DNP3 is the communication protocol widely used for the interoperability between control devices in the power utility industry. DNP3 has been implemented from physical layer to network layer at the hardware level in order to reduce the computing load on the CPU. Verilog hardware description language (HDL) has been used for the DNP design. The designed DNP3 core is usable as one of the intellectual properties (IPs) and it is applicable to design System-on-a-Chip (SoC) for various industrial controllers, network gateway, etc. Other layers have been implemented using C programs on Hitachi H8/532 processor. The DNP3 has been implemented using field programmable gate array (FPGA) technology and the commercial feasibility of the proposed solution has been performed through the communication test using DNP Master Simulator. Finally, the application specific IC (ASIC) for the DNP3 was developed and fabricated by the 0.8 micron Gate Array process technology of Hynix Semiconductor.

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