Abstract SiC is suitable for power devices and high quality SiC epitaxial layers having a high breakdown voltage are needed and thick epilayer is indispensable. In this study, we used the close space technique (CST) method which enable us to obtain thick epitaxial layers faster. Source material used was 3C–SiC polycrystalline plate with high purity and 4H–SiC with 8° off (0001) toward 11 2 ̄ 0 was used for the substrate. Step-bunching was strongly affected by pressure during crystal growth. The carrier concentration of epilayer decreased when a lower pressure was employed. Schottky diode was also made.