Frequency synthesizer is one of the most versatile component and heart of any system. It is used to correct the phase & frequency error so that the signal coming from the different part of the circuit or from the wireless medium does not cause any attenuation or distortion due to frequency dependent or phase dependent error. Present days the Frequency Synthesizer is also used for the wireless communication in the GHz range to correct the phase and frequency error as well as provide synchronization with low locking time, reduced skew and jitter. The frequency synthesizer is used inside a processor to provide the clock synchronization, clock recovery. Due to all above important application in the Analog and mixed signal as well as in digital signal analysis there is a necessity of a Frequency synthesizer with higher Capture range low lock time and with a low settling time. The design of given Frequency synthesizer is done in the 90nm (GPDK 090) process technology in CADANCE virtuoso Analog design environment. To detect the phase and frequency error for any unsymmetrical pulse the voltage based phase frequency detector is used in the design. Voltage controlled oscillator is also a very important part which decide the range of frequency synthesizer. The VCO used here is a current starved Ring oscillator which consumes a very low power. The loop filter is an important component that decides the Dynamic response of the frequency synthesizer. The rise time damping ratio, settling time, bandwidth and output signal to noise ratio of the circuit. The loop filter used here is a passive lead lag filter which is designed with the resistor and capacitor. The layout of the frequency synthesizer is done in the CADANCE virtuoso XL layout editor and different type of simulation is done in the spectre simulator. The power consumed in the frequency synthesizer is 0.22091 m watt at 1.2 V supply voltage and the lock time is 220 ns. The divider is a very important part which made the frequency synthesizer circuit tuneable in a wide range of input frequency so for this purpose we designed it programmable which divide in N/N+1 ratio.