Experience in Validation of PowerPCTM Microprocessor Embedded Arrays
- Authors
- Type
- Published Article
- Journal
- Journal of Electronic Testing
- Publisher
- Kluwer Academic Publishers
- Publication Date
- Aug 01, 1999
- Volume
- 15
- Issue
- 1-2
- Pages
- 191–205
- Identifiers
- DOI: 10.1023/A:1008352805631
- Source
- Springer Nature
- Keywords
- License
- Yellow
Abstract
Design validation for embedded arrays remains as a challenging problem in today's microprocessor design environment. Although several methods for validating embedded arrays have been proposed, not much has been done to characterize the strengths and weaknesses of these methods. This paper provides a comprehensive study of various design validation approaches adopted at the Somerset PowerPC Design Center in the past, including methods from both formal verification and test generation. Effectiveness of these approaches will be measured based on automatic design error injection and simulation at both gate and transistor levels. Experience of using different validation approaches on recent PowerPC microprocessor arrays will be analyzed and discussed.
