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Enhancing Hardware Security: A Comprehensive Analysis of Threats, Countermeasures, and Future Trends

Authors
  • Kaur, Inderpreet
Publication Date
Jan 01, 2023
Source
eScholarship - University of California
Keywords
Language
English
License
Unknown
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Abstract

The rapid expansion of digital technologies and interconnected systems has brought about an unprecedented need for safeguarding sensitive information against an array of hardware security threats. Among these threats are Hardware Trojan insertion, Reverse Engineering Side-Channel Attacks, and SAT attacks, which pose substantial risks to the confidentiality and integrity of various devices, ranging from smart cards to cloud computing infrastructures. This thesis presents a comprehensive examination of these security threats, encompassing their underlying principles, attack methodologies, and existing countermeasures, with a specific focus on analyzing the effectiveness of countermeasures and exploring potential future trends. To address these hardware security challenges, the thesis surveys current state-of-the-art AI/ML hardware accelerators, evaluating their resilience to hardware errors and mitigation strategies, while advocating for a multi-faceted approach to ensuring hardware system integrity. Additionally, the study addresses the evolution and impact of side-channel attacks, elucidating the exploitation of power consumption patterns, fault injection techniques, and physical characteristics of systems. The research proposes robust countermeasures and security-aware Electronic Design Automation (EDA) tools, leveraging STT-MRAM-based LUTs and routing-based obfuscation to design reconfigurable and interconnected logic blocks, offering reliable, low-power, and SAT-hard instances. Additionally, an EDA tool flow is established for automating the placement of lock blocks and optimizing security, achieving enhanced protection with minimal power and area overhead. Furthermore, the study highlights the importance of verification methodologies, particularly the Universal Verification Methodology (UVM), for checking design specifications. By providing a comprehensive overview of hardware security threats and their corresponding countermeasures, this thesis contributes to the development of more secure hardware designs, underscoring the necessity of a multi-faceted approach to safeguarding hardware system integrity.

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