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End-to-end Power Optimization of Circuits for Analog Coherent Optical Links

Authors
  • ANDRADE, HECTOR
Publication Date
Jan 01, 2022
Source
eScholarship - University of California
Keywords
Language
English
License
Unknown
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Abstract

Data centers today account for about 2.5 % of the total electricity usage in the United States. The portion of that power that is consumed by the internal network is increasing dramatically, as server-to-server traffic grows over 23 % every year. As aresult, there is great demand for scalable power-efficient intra data center (IDC) optical communication links. IDC links today are based on intensity-modulation direct-detection modulation formats (IMDD). Thus far, the scaling of IMDD links has been achieved by increasing the number of signal amplitude levels, by moving to higher baud rates, and by adding multiple wavelengths or fibers. However, each of these scaling paths is severely constrained. Whereas IMDD systems only utilize the intensity of signal, coherent detection (CD) also leverages the two polarizations and two quadratures of the fiber optic channel, and thus is more scalable. CD also improves sensitivity by up to 20 dB by mixing the received signal with a strong local oscillator. CD has been employed in long-haul links for many years, yet these systems rely on power-hungry high-speed analog-to-digital converters (ADC) and digital signal processing (DSP) and thus may be unsuitable for IDC links. A compelling alternative to DSP-based CD is analog coherent detection (ACD), in which polarization demultiplexing, carrier recovery, and phase demodulation are performed using analog circuits. This work focuses on the co-design of analog circuits and opto-electric devices that enable low-power ACD-based IDC links. First, a discussion of a proposed next-generation ACD IDC link architecture is outlined as motivation for the low-power circuit designs. Three monolithic 50 Gb/s opto-electric receiver topologies in SiGe BiCMOS technology are analyzed and compared. Then, a 100 Gb/s QPSK hybrid receiver in 45 nm CMOS is described. The co-design of a driver 56 Gb/s and traveling-wave Mach-Zehnder modulator (TW-MZM) is also presented. Finally, the thesis describes a TW-MZM equalization technique based on a tunable termination mismatch.

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