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An Interleaving Track & Hold with 7.6 ENOB @ 1.6 GS/s in 0.12 µm CMOS

STW Technology Foundation
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A 1.6 GS/s Track and Hold circuit that produces 16 interleaving, 100 MS/s voltage buffered output signals is presented. The achieved SFDR for a 950 MHz full scale input signal is 50 dB. Phase alignment is 0.4 ps RMS and aperture uncertainty is 1 ps RMS. The chip includes two Analog to Digital Converters and a Switching Matrix to accommodate measurement of all sampled output signals and their timing relation. Chip area is 0.14 mm2 excluding the AD Converters. The chip is made in a 0.12 µm, 1.2 V CMOS Process. Power consumption of the interleaving T/H circuit is 32 mW.

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