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Overview of the Cortex-M3-Chapter 2

Elsevier Inc.
DOI: 10.1016/b978-075068534-4.50008-7


Publisher Summary This chapter provides an overview of the Cortex-M3. The Cortex-M3 is a 32-bit microprocessor. It has a 32-bit data path, a 32-bit register bank, and 32-bit memory interfaces. The processor has a Harvard architecture, which means it has a separate instruction bus and data bus. This allows instructions and data accesses to take place at the same time, and as a result of this the processor performance increases because data accesses do not affect the instruction pipeline. This feature results in multiple bus interfaces on the Cortex-M3, each with optimized usage and the ability to be used simultaneously. The Cortex-M3 processor includes a number of fixed internal debugging components. These components provide debugging operation supports and features such as breakpoints and watchpoints. In addition, optional components provide debugging features such as instruction trace and various types of debugging interfaces. The Cortex-M3 processor has two modes and two privilege levels. The operation modes (thread mode and handler mode) determine whether the processor is running a normal program or running an exception handler like an interrupt handler or system exception handler. The privilege levels (privileged level and user level) provide a mechanism for safeguarding memory accesses to critical regions as well as providing a basic security model. Additionally, the Cortex-M3 processor includes a number of debugging features such as program execution controls, including halting and stepping, instruction breakpoints, data watchpoints, registers and memory accesses, profiling, and traces.

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