Publisher Summary On-chip communication architectures have numerous sources of delay due to signal propagation along the wires, synchronization, transfer modes, arbitration mechanisms for congestion management, cross-bridge transfers, and data packing/unpacking at the interfaces. These communication delays can significantly influence the performance of system-on-chip (SoC) applications, and are in fact, a major cause of bottlenecks in many designs. It is therefore important to consider these delays when exploring SoC applications to get an accurate estimation of the system performance. This chapter discusses the three major types of performance models used for communication architecture exploration. The static estimation approaches assume that computation and communication in a SoC design can be statically scheduled, which is not always true. Static approaches are also unable to predict dynamic component delays as well as dynamic delays arising due to arbitration and traffic congestion, cache misses, burst interruptions, interface buffer overflows and the effect of advanced bus features. This chapter discusses hybrid communication architecture performance estimation approaches and dynamic (simulation-based) performance estimation models.