Abstract All synchronous serial data transmission systems have to be able to divide the incoming data stream into individual bits at the receiving end of the data link. As it is generally impossible to provide a separate clock channel from the transmitter to the receiver, synchronous systems invariably encode the transmitted data in such a way that the clock signal can be recovered from the received data. A popular method of encoding a data signal and clock signal is called phase encoding, or Manchester encoding. The transmitted signal is forced to make a transition at the centre of each data cell. A logic ‘1’ is transmitted by a ‘0-to-1’ transition and a ‘0’ is transmitted as a ‘1-to-0’ transmission. Until recently Manchester encoders and decoders had to be constructed out of a handful of TTL logic. The widespread application of synchronous serial transmission systems (in particular the growth of LANs based on Ethernet) has encouraged semiconductor manufacturers to produce single-chip Manchester encoder/ decoders. This application note from AMD looks at the design of a Manchester encoder based not on a custom chip but on AMD's PALC22V10 programmable array logic element. Modem programmable logic elements are able to synthesize circuits that would have required ten or more SSI and MSI packages and have taken up a large area on a PCB. The PALC22V10 contains both the combinational logic and the sequential logic elements necessary to design functional logic blocks such as Manchester encoders. A.C.