Abstract This paper deals with a design for testability strategy for the SYCO control section compiler developed in the IMAG/TIM3 laboratory. The SYCO control section compiler translates high level descriptions into mask level specification for hierarchical control sections, which are composed of a stack of control section slices, each organized around a PLA. The proposed design for testability scheme is called UBIST and ensures a high quality for all tests needed for integrated circuits (i.e. on-line and off-line tests). We outline the concept of UBIST and show how we modify the SYCO control section compiler's data structure and its automatic layout synthesizer to generate automatically and efficiently UBIST control sections.