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On-line testing for VLSI: state of the art and trends

Authors
Journal
Integration the VLSI Journal
0167-9260
Publisher
Elsevier
Publication Date
Volume
26
Identifiers
DOI: 10.1016/s0167-9260(98)00028-5
Keywords
  • On-Line Testing
  • Self-Checking Circuits
  • On-Line Current Monitoring
  • Perturbation Hardened Circuits
  • Soft Errors
  • Deep Submicron Scaling
  • Fail-Safe Circuits
  • Hardware Fault Tolerance
Disciplines
  • Communication
  • Medicine

Abstract

Abstract This paper discusses the state of the art and future trends of on-line testing techniques for VLSI. It cautions that emerging technological constraints and application requirements will expend dramatically the use of these techniques. In particularly, various industrial (e.g. railway control, satellites, avionics, telecommunications, control of critical automotive functions, medical electronics, industrial control, etc.), have increasing needs of various on-line testing features. Some of these applications concern mass production and should support the standardization of such techniques and the development of commercial CAD tools supporting them. Furthermore, drastic device shrinking and increasing operating speeds that accompany the technological evolution to deeper submicron, reduces significantly the noise margins and increases dramatically the soft error rates. As a consequence, technological progress will be blocked quickly if no particular actions are undertaken to cope with increasingly high soft-error rates. The paper will discuss these emerging requirements and problems and describe on-line testing techniques that could provide adequate solutions.

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