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Imaging of the lateral GOI-defect distribution in silicon MOS wafers with lock-in IR-thermography

Authors
Journal
Materials Science in Semiconductor Processing
1369-8001
Publisher
Elsevier
Publication Date
Volume
4
Identifiers
DOI: 10.1016/s1369-8001(00)00145-1
Keywords
  • Goi
  • Gate Oxide Integrity Defects
  • Cop
  • Ir-Thermography
  • Whole Wafer Mapping

Abstract

Abstract Yield and reliability of MOS devices are strongly affected by crystal-originated particles which may generate gate oxide integrity (GOI) defects. For the semiconductor industry it is highly desirable not only to measure the density, but also to image the lateral distribution of GOI-defects. A novel technique to image GOI defects across large gate areas has been developed. First, a low-ohmic bias pulse is used to break down nearly all GOI defects in a large-area MOS structure. Then a periodic bias of typically 2 V is applied and the local temperature variation caused by the leakage current through the broken GOI defects is imaged by lock-in IR-thermography. This technique has been used to image the GOI defect distribution across 8′′ Czochralski wafers. Various lateral variations of the defect distribution have been confirmed.

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