Abstract Continuous scaling of transistor feature size rapidly increases the effect of intermittent faults. These faults manifest as timing violations due to the combined effects of process variation, circuit wear-out, and variation in environmental conditions. In this paper, we combine all critical sources of intermittent faults in a comprehensive framework. Our experiments with the MIPS-789 processor reveal that at the 22nm technology node, the combined effect of all the factors can degrade the delay by 2.5X. Such gross delay degradation extending more than two cycles can render many recently proposed time borrowing techniques ineffective. We analyze three architectural techniques to mitigate intermittent faults and evaluate them using full system architectural simulation.