This work presents the implementation of the continuous-time quadrature bandpass sigma-delta modulators (CT-QBP SDMs). CT-QBP SDMs is well suited for low-IF receivers due to some significant advantages over other implementations. Firstly, the possible design methodologies have been defined and compared. The proposed inverse method is desirable for the design of CT-QBP SDM. Starting from CT loop filter optimization, the equivalent noise shaping transfer function is finally calculated and its stability margin is estimated. Because of the optimization in the CT-domain, this method gives to designer lots of flexibilities for circuit design in CT domain, while decreasing circuit complexity and chip area. In order to estimate the modulator performances, the simulation method by Matlab code has been presented which is an extension of Delta-Sigma Toolbox. Secondly, the polyphase filter with capacitive feedforward summation have been proposed. The proposed topology is suited for low power and low voltage applications. Feedforward coefficients are obtained as the ratios of the feedforward capacitors to last integrating capacitor and the summation is implemented by feedforward capacitors in the last complex integrator, without extra active components. The proposed polyphase filters contains the conventional cross-couplings for moving poles to center frequency, and the proposed compensation cross-couplings for moving zeros caused by capacitive feedforward. Thirdly, the non-ideal effects of CT-QBP SDMs have been estimated and their compensation solutions have been proposed. Finite GBW of the amplifiers affect stability and frequency shifting to a wanted center frequency of the polyphase filters. In order to ensure the stability, the use of a lossy complex integrator is desirable. The deviation from the center frequency can be decreased by inserting the transconductors in the virtual ground nodes of the amplifiers. Excess loop delay seriously results in unstability and degradation of the SNR. In order to compensate its effect, the additional feedback DAC with unit delay and the feedforward complex compensation coefficient can be used. Mismatched loop delay of the real and imaginary paths makes an aliased noise power in the passband and results in SNR degradation. It can be completely compensated by using D-latches in the feedback paths and the excess loop delay compensation scheme. Clock jitter severely reduces the modulator performance. The degradation of the SNR caused by clock jitter depends on the number of the output bit transitions. In order to reduce the jitter-induced noise, an optimized noise shaping transfer function and modified feedback DAC analog waveforms can be applied. The mismatch of the unit elements in the multi-bit DAC bank causes a nonlinear error of the modulator. In order to reduce the nonlinearity, the first-order complex mismatch shaper have been proposed which is centered at any center frequency. Lastly, two design prototypes have been shown as examples; one is high resolution, medium bandwidth CT-QBP SDM for GSM/EDGE low-IF receiver, and the other is reconfigurable multi-mode wideband CT-QBP SDM for GPS/Galileo low-IF receiver. The test chips were designed in a 0.25 um CMOS technology. For GSM/EDGE application, the measurement results demonstrate a SFDR of 96.0 dB and an image rejection of 75.8 dB at 70 kHz and -3 dBFS input signal. The DR of 90.3 dB was achieved with a peak SNDR of 86.8 dB. The measured power dissipation is less than 2.7 mW at 1.8 V supply voltage. For GPS/Galileo application, the designed modulator achieved a peak SNDR of 52.9dB for GPS and 48.4 dB for Galileo application.