The combination of non-volatility, fast access time and endurance in MRAM technology paves the path toward an universal memory. Although an expanding attention is given to two-terminal Magnetic Tunnel Junctions (MTJ) based on Spin-Transfer Torque (STT) switching as the potential candidate for future memories, its reliability is significantly decreased because of the common writing/reading path. Three-terminal MTJ based on Spin-Orbit Torque (SOT) approach revitalizes the hope of an ultimate MRAM. It represents a pioneering way to triumph over current two-terminal MTJs by separating the reading and the writing path. This paper represents simulation results of the first compact model which describes the SOT-MTJ device based on recently fabricated samples. The model is developed in Verilog-A language, implemented on industrial CAD platform and validated by electrical simulations. Many experimental parameters are included in the model in order to enhance simulation accuracy. Based on simulations results, we show the capability of the model to be efficiently used to design hybrid MTJ/CMOS circuits.