The sidewall defects in selective epitaxial growth (SEG) of silicon were characterized and the nature of these defects was investigated. Electrical characterization of the sidewall defects was performed using diodes fabricated in structures using the SEG of silicon and chemical‐mechanical polishing. Diodes were fabricated with various perimeter to area ratios to extract the bulk and sidewall saturation current densities and ideality factors in as‐grown SEG diodes and reoxidized sidewall SEG diodes. Transmission electron microscopy was used to show that nitrogen annealing of the sample with the sidewall oxide removed exhibited a dramatic decrease in the sidewall defects as compared to the sample with the sidewall oxide present during the anneal. The generation of the defects was attributed to stress due to the mismatch in thermal expansion coefficients of oxide and silicon and a model describing the generation of these defects was formulated and described. © 1995 American Vacuum Society.