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The fastest sample-and-hold circuit

Authors
Journal
Microelectronics Journal
0026-2692
Publisher
Elsevier
Publication Date
Volume
21
Issue
3
Identifiers
DOI: 10.1016/0026-2692(90)90045-5

Abstract

Abstract In a normal fast sample-and-hold circuit (SHC), the sample rate is primarily limited by the acquisition time during which the hold capacitor is charged to the input level. This paper describes a new circuit configuration with which the sample rate is determined exclusively by the hold time. The SHC itself corresponds to a dummy-switch-compensated SHC with respect to clock-feedthrough.

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