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Energy-balance modeling of short channel single-GB thin film transistors

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Microsoft Word - 06_Walker.doc Int. J. Computational Science and Engineering, Vol. 2, Nos. 3/4, 2006 Copyright © 2006 Inderscience Enterprises Ltd. 148 Energy-balance modelling of short channel single-GB thin-film transistors Philip M. Walker* Microelectronics Research Centre, University of Cambridge, Cambridge CB3 0HE, UK E-mail: [email protected] *Corresponding author Hiroshi Mizuta School of Electronics and Computer Science, University of Southampton, Southampton SO17 1BJ, UK Department of Physical Electronics, Tokyo Institute of Electronics, Tokyo 152-8552, Japan E-mail: [email protected] Abstract: In this paper, we have investigated the effect of a single Grain Boundary (GB) on the performance of decananometer-scale Thin Film Transistors (TFTs) by using the calibrated energy balance transport model and a continuous trap state distribution at the GB. We have found that the GB potential barrier suppresses the subthreshold slope and leakage current in devices, where the DIBL effect and punchthrough currents significantly degrade device performance. We have also found that the drift-diffusion model underestimates the drain current in the single-GB TFT and the velocity overshoot effect becomes significant in the short channel regime. Inclusion of trap-to-band and band-to-band tunnelling models into our simulations have shown that the subthreshold leakage current has a significant field dependence in the negative gate bias regime. Keywords: poly-silicon; grain boundary; energy-balance modelling; thin-film transistor. Reference to this paper should be made as follows: Walker, P. M. and Mizuta, H. (2006) ‘Energy-balance modelling of short channel single-GB thin-film transistors’, Int. J. Computational Science and Engineering, Vol. 2, Nos. 3/4, pp.148–157. Biographical notes: P.M. Walker is a Research Student at the University of Cambridge. His PhD research has been to study the potential applications of polycrystalline silicon for us

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