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Design of IO Processor for Software Implementation of Data IO Intensive H.264 Decoder Functional Block

서울대학교 대학원
Publication Date
  • H.264
  • Avc
  • O 프로세서
  • Programmable Dma
  • O Processor
  • Reconstruction
  • Programmable Dma
  • Reference Frame Loader
  • Reconstruction
  • Reference Frame Loader
  • Communication


In this paper, I/O-specific processor architecture for data I/O intensive functional blocks is proposed for software implementation of video decoders. With the proposed architecture, an H.264/AVC decoder implemented and evaluated. In the proposed architecture, a function block is divided into three parts for an input a core computation, and an output. To enhance the performance, they are pipelined and performed in parallel. Furthermore, they can be optimized with application-specific instructions such as SIMD instructions to meet the performance requirements. Each component has several channel interfaces to other components to obtain high communication performance. Three function blocks for reconstruction, reference frame loading, and deblocking in a H.264 decoder are implemented with the proposed approach. We found that this approach is effective for the blocks for reconstruction and reference frame loading even though the reference block requires about two performance compared to the reconstruction block. In contrast, because the core computation part of the deblocking block requires substantially large computation, compared to its input and output parts, we found that it is difficult to get an performance improvement with this approach without outing a SIMD implementation of the core part, which has not covered in this thesis. * Note: The text above is the abstract of the thesis. You can use the full-text by clicking the "Link" (URL) of item record and the viewer program will be installed automatically. In case of having problem with the viewer program installation, please download it manually using this url

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