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Cache Aware Dynamics Data Layout for Efficient Shared Memory Parallelisation of EUROPLEXUS

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Publication Date
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HAL-UPMC
Keywords
  • Europlexus
  • Shared Memory
  • Cache-Aware Data Layout
  • Parallel Programming
  • [Info.Info-Dc] Computer Science [Cs]/Distributed, Parallel, And Cluster Computing [Cs.Dc]
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Abstract

Parallelizing industrial simulation codes like the EUROPLEXUS software dedicated to the analysis of fast transient phenomena, is challenging. In this paper we focus on the efficient parallelization on a multi-core shared memory node. We propose to have each thread gather the data it needs for processing a given iteration range, before to actually advance the computation by one time step on this range. This lazy cache aware layout construction enables to keep the original data structure and leads to very localised code modifications. We show that this approach can improve the execution time by up to 40% when the task size is set to have the data fit in the L2 cache.

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