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Allocation of multiple precision behaviors for maximal bit level reuse of hardware resources

Authors
Journal
Journal of Systems Architecture
1383-7621
Publisher
Elsevier
Publication Date
Volume
49
Identifiers
DOI: 10.1016/s1383-7621(03)00099-7
Keywords
  • High Level Synthesis
  • Bit Level Allocation
  • Multiple Precision Specification
Disciplines
  • Computer Science

Abstract

Abstract This paper proposes an allocation algorithm able to perform the combined resource selection and operation binding of multiple precision specifications. The common operative kernel of additive specification operations is extracted, and an allocation independent of the operations widths is performed. As a result, one operation may be executed over either one wider functional unit, or a set of linked narrower functional units. This allocation approach maximizes the bit level reuse of hardware resources, thus substantially reducing the area of the final implementations. The maximum number of bits computed per cycle becomes the sole determining factor affecting the cost of circuits, in contrast with circuits proposed by conventional algorithms which are influenced by the number and widths of the operations executed in every cycle. Additionally an analytical method is presented to estimate the amount of area potentially saved in comparison with conventional allocation algorithms.

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