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New nodal design for high throughput data vortex optical interconnection network

Optical Switching and Networking
DOI: 10.1016/j.osn.2013.05.004
  • Data Vortex
  • Packet Switch
  • Interconnection Network
  • Design


Abstract This paper proposes a new three input nodal structure within the data vortex packet switched interconnection network. With additional optical switches, the modified architecture allows for two input packets in addition to a buffered packet to be processed simultaneously within a routing node. A much higher degree of parallel processing is allowed in comparison to previously proposed enhanced buffer node with two input processing or the original network node with single input processing. Unlike the previous contention prevention mechanism, the new network operates by introducing the packet blocking within the node if no exit path is available. This eliminates the traffic control signaling and the strict timing alignment associated with the routing paths which simplifies the overall network implementation. This study shows that both data throughput and the latency performance are improved significantly within the new network. The study compares the three input node with the two input node as well as the original single input data vortex node. Due to additional switch count and nodal cost, networks that support the same I/O ports and of the same cost are compared for a fair comparison. The limitation introduced by the blocking rate is also addressed. The study has shown that under reasonable traffic and network condition, the blocking rate can be kept very low without introducing complex controls and management for dropped packets. As previous architectures require operation under saturation point, the proposed architecture should also operate at reasonable level of network redundancy to avoid excessive packet drop. This study provides guidance and criteria on the proposed three input network design and operation for feasible applications. The proposed network provides an attractive alternative to the previous architectures for higher throughput and lower latency performance.

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