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Composite ULP diode fabrication, modelling and applications in multi-VthFD SOI CMOS technology

Authors
Journal
Solid-State Electronics
0038-1101
Publisher
Elsevier
Publication Date
Volume
48
Issue
6
Identifiers
DOI: 10.1016/j.sse.2003.12.016
Keywords
  • Soi
  • Low Power
  • Diode
  • Memory
  • Mtcmos

Abstract

Abstract We present new SOI basic circuit cells architectures for ultra-low power (ULP) applications that use transistors in very weak inversion. These cells take advantage of the possibility to obtain multi-threshold transistors in fully depleted (FD) SOI CMOS with no additional cost. In particular, a new composite ULP diode is proposed and modelled. It has been fabricated on 0.18 and 2 μm FD SOI technologies and demonstrated a reduction of leakage currents by four orders of magnitude compared to standard MOS diode implementation. We demonstrate that the ULP diode can be used to realize memory cells that present strongly reduced static power consumption compared to standard SRAM cells and can work under 0.5 V supply voltage. As particular application, simulations of ULP memory latches used as level-keepers in MTCMOS circuits to maintain information on floating nodes during standby mode demonstrate static power savings of 20% when compared to the best traditional schemes with comparable speed performance. Finally, measurements show that the new proposed ULP cells keep functionality at high temperature.

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