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BDD Based Logic Synthesis of MEM Relay Circuits

  • Jiang, Mingzhe
Publication Date
Jan 01, 2013
eScholarship - University of California
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As CMOS scaling begins to reach its fundamental limits, micro-electro-mechanical (MEM) relays provide an attractive option for improvements in energy efficiency due to their low leakage and nearly ideal I-V characteristics. However, mechanical actuation of MEM relays introduces significantly more delay than traditional CMOS electrical delay. In order to mitigate this effect, custom relay circuits are designed manually to make all mechanical actuations to happen simultaneously. A Karnaugh map-based synthesis tool was attempted to automate this design process. However, this synthesis tool has computational complexity growing exponentially in terms of the number of inputs, making it impractical for larger combinational circuit. Therefore, a synthesis algorithm based on binary decision diagram (BDD) has been investigated and developed in this work to conquer the computational complexity issue. Optimizations are performed at BDD level to reduce the number of devices needed in the design. In addition, circuits with multiple mechanical delays can also be generated by using BDD decomposition algorithm. The output is a relay netlist which can be ported to commercial place and route tools creating a simple automated MEM relay circuit design flow.


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