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Fast-locking CDR circuit with autonomously reconfigurable mechanism

Authors
Journal
Electronics Letters
0013-5194
Publisher
Institution of Electrical Engineers
Publication Date

Abstract

A new fast-locking scheme is applied to a clock and data recovery (CDR) circuit based on a phase-locked loop. Locking time is reduced by using an autonomously reconfigurable charge pump and loop filter. A 1.25 Gbit=s prototype CDR circuit has been implemented in a 0.18 mm CMOS technology.

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