Abstract Signal processing algorithms and architectures that support high-speed throghput requirements in computationally demanding areas are described in this paper. Multi-level parallelism is obtained by combining features of algebraic-integer number representation and concurrency of systolic arrays. Regularity and modularity of architecture supports VLSI design criteria. The area-time complexity of the design is given for array implementing finite impulse response filtering and matrix arithmetic. Pipelined array allows data cycle frequency of 20MHz.