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Concurrent architectures for real-time signal processing

Authors
Journal
Microprocessing and Microprogramming
0165-6074
Publisher
Elsevier
Publication Date
Volume
28
Identifiers
DOI: 10.1016/0165-6074(90)90180-h
Disciplines
  • Computer Science
  • Design
  • Mathematics

Abstract

Abstract Signal processing algorithms and architectures that support high-speed throghput requirements in computationally demanding areas are described in this paper. Multi-level parallelism is obtained by combining features of algebraic-integer number representation and concurrency of systolic arrays. Regularity and modularity of architecture supports VLSI design criteria. The area-time complexity of the design is given for array implementing finite impulse response filtering and matrix arithmetic. Pipelined array allows data cycle frequency of 20MHz.

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