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Power reduction methods for NMOS dynamic random access memories

Authors
Journal
Microelectronics Reliability
0026-2714
Publisher
Elsevier
Publication Date
Volume
28
Issue
6
Identifiers
DOI: 10.1016/0026-2714(88)90286-7
Disciplines
  • Design

Abstract

Abstract Power reduction methods for NMOS dynamic random access memories are proposed which reduce power dissipation. As the bit density increases in NMOS dynamic random access memories the power dissipation increases. A major consideration in the design of megabit dynamic random access memories is the power supply voltage. The power supply voltage mainly depends upon the following factors: power dissipation; reliability, such as high field effects due to small device size; memory cell operating margin. Power dissipation in decoders and 1 megabit NMOS dynamic random access memory chips are discussed. The basic properties of the proposed methods and a prototype VLSI implementation are discussed. In order to meet user power supply requirements, the proposed power reduction methods are useful for future megabit NMOS dynamic random access memories.

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