Recent growth in applications related to the Internet of Things, has introduced new challenges to the design of integrated circuits. Accuracy of sensors, power consumption, speed, and sensitivity to internal and external noise sources are some of the challenges addressed in this dissertation. A delta-sigma circuit architecture is designed to measure resistance with an accuracy of -/+ 1% over a range of four orders of magnitude. This performance is verified through both analog and mixed-signal simulation and chip measurement. A novel compensation technique is developed and simulated to reduce the supply sensitivity of an LC oscillator. An improvement of 85% is verified based on simulations of jitter and frequency variation. A new architecture is proposed for design of oscillators, based on a double-ladder periodic structure, whose behavior is less sensitive to the output termination resistance as compared to conventional oscillators. The advantages of the designed oscillator is verified compared to conventional LC and single-ladder structure oscillators. The design is optimized based on phase noise and power consumption.