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Three-dimensional integration scheme with a thermal budget below 300 °C

Authors
Journal
Sensors and Actuators A Physical
0924-4247
Publisher
Elsevier
Publication Date
Volume
139
Identifiers
DOI: 10.1016/j.sna.2007.04.032
Keywords
  • Silicon Fabrication Technology
  • Microsystems
  • 3D-Stacking
  • Chip Stack
  • Vertical Integration
  • Through Chip Via

Abstract

Abstract A solution for the wiring problem in highly complex and embedded systems is the technology of three-dimensional integration. This approach allows a high interconnect density between two or more chips with very short signal or power lines. With the chip stacking concept shown here, a via density of up to 4400 vias per mm 2 is obtained for a chip thickness of 10 μm. However, in this technology it seems also important to implement already fully processed CMOS and memory circuits and thus only frontend and backend processes are considered. This limits the maximum processing temperature to 300 °C to avoid any degeneration in pre-processed circuits. First results show very low leakage currents as well as very low through resistances.

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