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Enabling design and simulation of massive parallel nanoarchitectures

Authors
Journal
Journal of Parallel and Distributed Computing
0743-7315
Publisher
Elsevier
Volume
74
Issue
6
Identifiers
DOI: 10.1016/j.jpdc.2013.07.010
Keywords
  • Nanoarchitecture
  • Massive Parallelism
  • Nanofabric
  • Cad Design Tool
  • Place And Route
  • Simulations
  • Device And Parasitic Extraction
  • Table Model
Disciplines
  • Design
  • Physics

Abstract

Abstract A common element in emerging nanotechnologies is the increasing complexity of the problems to face when attempting the design phase, because issues related to technology, specific application and architecture must be evaluated simultaneously. In several cases faced problems are known, but require a fresh re-think on the basis of different constraints not enforced by standard design tools. Among the emerging nanotechnologies, the two-dimensional structures based on nanowire arrays is promising in particular for massively parallel architectures. Several studies have been proposed on the exploration of the space of architectural solutions, but only a few derived high-level information from the results of an extended and reliable characterization of low-level structures. The tool we present is of aid in the design of circuits based on nanotechnologies, here discussed in the specific case of nanowire arrays, as best candidate for massively parallel architectures. It enables the designer to start from a standard High-level Description Languages (HDLs), inherits constraints at physical level and applies them when organizing the physical implementation of the circuit elements and of their connections. It provides a complete simulation environment with two levels of refinement. One for DC analysis using a fast engine based on a simple switch level model. The other for obtaining transient performance based on automatic extraction of circuit parasitics, on detailed device (nanowire-FET) information derived by experiments or by existing accurate models, and on spice-level modeling of the nanoarray. Results about the method used for the design and simulation of circuits based on nanowire-FET and nanoarray will be presented.

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