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Dynamically reconfigurable hardware–software architecture for partitioning networking functions on the SoC platform

Authors
Journal
Journal of Systems and Software
0164-1212
Publisher
Elsevier
Publication Date
Volume
82
Issue
10
Identifiers
DOI: 10.1016/j.jss.2009.03.015
Keywords
  • System On Chip
  • Network Protocols
  • Hardware–Software Co-Design
  • Reconfigurable Hardware–Software Architecture
Disciplines
  • Design

Abstract

Abstract We present an issue of the dynamically reconfigurable hardware–software architecture which allows for partitioning networking functions on a SoC (System on Chip) platform. We address this issue as a partition problem of implementing network protocol functions into dynamically reconfigurable hardware and software modules. Such a partitioning technique can improve the co-design productivity of hardware and software modules. Practically, the proposed partitioning technique, which is called the ITC (Inter-Task Communication) technique incorporating the RT-IJC 2 (Real-Time Inter-Job Communication Channel), makes it possible to resolve the issue of partitioning networking functions into hardware and software modules on the SoC platform. Additionally, the proposed partitioning technique can support the modularity and reuse of complex network protocol functions, enabling a higher level of abstraction of future network protocol specifications onto the SoC platform. Especially, the RT-IJC 2 allows for more complex data transfers between hardware and software tasks as well as provides real-time data processing simultaneously for given application-specific real-time requirements. We conduct a variety of experiments to illustrate the application and efficiency of the proposed technique after implementing it on a commercial SoC platform based on the Altera’s Excalibur including the ARM922T core and up to 1 million gates of programmable logic.

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