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Stream computations organized for reconfigurable execution

Authors
Journal
Microprocessors and Microsystems
0141-9331
Publisher
Elsevier
Publication Date
Volume
30
Issue
6
Identifiers
DOI: 10.1016/j.micpro.2006.02.009
Keywords
  • Fpga
  • Reconfigurable
  • Scalability
  • Design Reuse
  • Streaming
  • System Architecture
  • Design Patterns
  • Pipe-And-Filter
  • Productivity
Disciplines
  • Computer Science
  • Engineering

Abstract

Abstract Reconfigurable systems can offer the high spatial parallelism and fine-grained, bit-level resource control traditionally associated with hardware implementations, along with the flexibility and adaptability characteristic of software. While reconfigurable systems create new opportunities for engineering and delivering high-performance programmable systems, the traditional approaches to programming and managing computations used for hardware systems (e.g., Verilog, VHDL) and software systems (e.g., C, Fortran, Java) are inappropriate and inadequate for exploiting reconfigurable platforms. To address this need, we develop a stream-oriented compute model, system architecture, and execution patterns which can capture and exploit the parallelism of spatial computations while simultaneously abstracting software applications from hardware details (e.g., timing, device capacity, and microarchitectural implementation details) and consequently allowing applications to scale to exploit newer, larger, and faster hardware platforms. Further, we describe hardware and software techniques that make this late-bound platform mapping viable and efficient.

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