Affordable Access

Publisher Website

Self-protection capability of integrated NLDMOS power arrays in ESD pulse regimes

Authors
Journal
Microelectronics Reliability
0026-2714
Publisher
Elsevier
Publication Date
Volume
51
Issue
12
Identifiers
DOI: 10.1016/j.microrel.2011.05.017
Disciplines
  • Mathematics

Abstract

Abstract This paper provides a review of most recent cycle of studies of NLDMOS-based power arrays, their operation in ESD regimes, self-protection capability as well as the methods and measures to improve the array robustness on the device structure, layout architecture and array composition levels. Effective practices of improving ESD robustness at the cell level and backend level are presented followed by topology optimization. Discussion is based upon ESD characterization supported both by device-circuit mixed-mode and 2.5D array level simulations data.

There are no comments yet on this publication. Be the first to share your thoughts.

Statistics

Seen <100 times
0 Comments

More articles like this

HBM and TLP ESD robustness in smart-power protecti...

on Microelectronics Reliability Jan 01, 1999

A novel on-chip ESD protection circuit for GaAs HB...

on Journal of Electrostatics Jan 01, 2003

ESD protection design for CMOS RF integrated circu...

on Microelectronics Reliability Jan 01, 2002

On-chip ESD protection design for integrated circu...

on Microelectronics Journal Jan 01, 2001
More articles like this..