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Delay-insensitive multi-ring structures

Authors
Journal
Integration the VLSI Journal
0167-9260
Publisher
Elsevier
Publication Date
Volume
15
Issue
3
Identifiers
DOI: 10.1016/0167-9260(93)90035-b
Keywords
  • Delay-Insensitive Circuits
  • Self-Timed Circuits
  • Vector Multiplier
  • Performance Analysis
  • Vlsi Design
Disciplines
  • Computer Science
  • Design

Abstract

Abstract This paper describes a set of simple design and performance analysis techniques that have been successfully used to design a number of non-trivial delay-insensitive circuits. Examples are building blocks for digital filters and a vector multiplier using a serial-parallel multiply and accumulate algorithm. The vector multiplier has been laid out, submitted for fabrication, and successfully tested. This design is described in detail to illustrate the design and the performance analysis techniques. The design technique is based on a data flow approach using pipelines and rings that are composed into larger multi-ring structures. For this restricted class of structures, it becomes possible — even for circuits of realistic size and complexity — to analyze the performance and establish an understanding of the bottlenecks. The paper combines a number of previously published results and techniques, and the main contribution of the paper is the comprehensive, integrated presentation of the material, including a thorough description of the vector multiplier design example.

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