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Trapped charge and stress induced leakage current (SILC) in tunnel SiO2layers of de-processed MOS non-volatile memory devices observed at the nanoscale

Authors
Journal
Microelectronics Reliability
0026-2714
Publisher
Elsevier
Publication Date
Volume
49
Identifiers
DOI: 10.1016/j.microrel.2009.06.016

Abstract

Abstract In this work, Conductive Atomic Force Microscope (CAFM) experiments have been combined with device level measurements to evaluate the impact of an electrical stress applied on MOS structures with a 9.8 nm thick SiO 2 layer for memory devices. Charge trapping in the generated defects and leakage current measured at the nanoscale have been correlated to the measurements obtained on fully processed MOS structures.

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