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Boolean neural network realization of an adder-subtractor cell

Authors
Journal
Microelectronics Reliability
0026-2714
Publisher
Elsevier
Publication Date
Volume
36
Issue
3
Identifiers
DOI: 10.1016/0026-2714(95)00086-0
Disciplines
  • Computer Science
  • Design
  • Mathematics

Abstract

Abstract A great deal of interest has emerged recently in the field of Boolean neural networks. Boolean neural networks require far less training than the conventional neural networks and have a variety of applications. They are also strong candidates for VLSI design. In this paper, a technique for learning representation of an adder-subtractor cell has been proposed. The technique can be exploited for the VLSI design of an arithmetic unit for a pipelined digital computer.

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